To make integrated circuits (ICs), such as memory devices and logic devices, having a high integration density the industry generally downscales the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs), and passive devices, such as semiconductor resistors and eFuses. Scaling achieves compactness and improves the operating performance in devices by shrinking the overall dimensions of the devices while maintaining the electrical properties of the devices. Generally, all the dimensions of a device are typically scaled simultaneously in order to optimize its electrical performance.
Silicided polysilicon eFuses and polysilicon resistors are widely used in today's semiconductor products because of their superior performance over many other solutions. These eFuses are known for a highly reliable silicide electromigration at acceptable current levels. Polysilicon resistors can outperform many other semiconductor resistors by means of a highly accurate resistivity, low temperature coefficiency and low parasitic capacitance. In many conventional CMOS device fabrication technologies, these eFuses and polysilicon resistors typically share a same polysilicon material, which is also used to create the gate electrode for a CMOS transistor. During patterning of the gate electrode structure, the bodies of the eFuses and resistors can also be created with the required dimensions of the polysilicon. In general, a polysilicon silicide wire having a minimum width is used for eFuse applications. The size of a resistor can be determined based on the basic specific resistance value of the polysilicon material and subsequent type and concentration of dopant material that can be incorporated into the resistor to adjust the resistance value. Also, both the eFuse and the resistor properties change dramatically whenever the gate electrode fabrication process changes affecting the gate height, the gate doping, and the gate integration. Further, certain conventional CMOS device fabrication technologies create electrical isolations such as Shallow Trench Isolations or local oxidation of silicon (LOCOS) to isolate devices electrically. Shallow Trench Isolations (STI) separate regions of two adjacent devices, minimizing the electrical interaction between the two devices and reducing the capacitive coupling or leakage between them. See, for example, U.S. Pub. Nos. US 2010/0019344A1, NOVEL POLY RESISTOR AND POLY EFUSE DESIGN FOR REPLACEMENT GATE TECHNOLOGY, BY Chuang et al, published Jan. 28, 2010. and US 2010/0059823A1, RESISTIVE DEVICE FOR HIGH-K METAL GATE TECHNOLOGY AND METHOD OF MAKING, by Chung et al, published Mar. 11, 2010, which are both incorporated in their entireties herein by reference.